1. Field of the Invention
The present invention generally relates to real-time microprocessor or digital signal processor based systems and, more particularly, to testing and debugging of the real-time microprocessor or digital signal processor embedded in system-on-chip (SOC) devices.
2. Background Description
Real-time microprocessors or digital signal processors based systems pose special problems which are not present in traditional microprocessor based systems. One of the major problems is in testing and debugging these systems. Particularly, as digital signal processing (DSP) computer systems are integrated in a single chip with other system components, e.g., memory blocks and data buses, the integration introduces problems in debugging and emulation schemes. These problems come from a variety of factors, including increase of the system clock speed, a system design based on a xe2x80x9cvery high speed integrated circuit (VHSIC) hardware description languagexe2x80x9d (VHDL) core and multiple memory blocks embedded in the chip.
Traditional emulator schemes for debugging and testing the real-time signal processors, e.g., the joint test action group (JTAG) system, have relied on the ability to start and stop the processor by using a variety of mechanisms, which includes setting software breakpoints and single stepping through the machine code. A major drawback of the traditional emulation schemes for the real-time microprocessor or digital signal processor based systems is that the processor must be stopped once a breakpoint is reached or the instruction is executed. This imposes significant problems in real-time systems. For example, in the situation where a real-time DSP system is used as a digital motor controller, stopping the processor could drive an invalid control signal to the actuator, which may cause a disastrous result.
Hardware debug of real-time DSP systems presents additional problems. The architecture of modern DSP systems includes multiple address and data busses for both program and data memory spaces. Numerous combinations of these busses could be active at any one time. Particularly, in xe2x80x9csystem-on-chip (SOC)xe2x80x9d situations where the memory is located on the same chip as the processor core, it is impossible to observe activities of these address/data busses, and, therefore, it has not been possible to debug a real-time microprocessor or DSP system by using the traditional emulation methods.
It is therefore an objective of the present invention to provide non-obtrusive real-time debugging and testing scheme for real-time signal processing systems based on a system-on-chip (SOC) architecture.
Another objective of the present invention is to provide a on-chip logic analysis system for testing and debugging for the SOC signal processing systems without interrupting operations thereof.
Another objective of the present invention is to provide a signal processing system implemented in a single chip with a non-obtrusive real-time data acquisition capability.
Another objective of the present invention is to provide an on-chip VHSIC hardware description language (VHDL) macro with non-obtrusive real-time data acquisition capability.
Another objective of the present invention is to provide a high speed serial interface between a target system and a host system of an logic analysis system with low pinout chips.
Another objective of the present invention is to provide a multiplexing scheme for an logic analysis system to record memory buses at a higher bit stream.
Additional objectives, advantages and other features of the present invention will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by an on-chip logic analysis (OCLA) system which comprises a single chip device internally including a signal processing unit, a plurality of memory blocks and a data capturing unit. A host unit is externally provided to the single chip device and generates control signals to control the data capturing unit. The data capturing unit captures data processed by the signal processing unit in response to the control signals from the host unit and transfers the captured data to the host unit without interrupting operations of the signal processing unit.
Another aspect of the present invention is an on-chip very high speed integrated circuit (VHSIC) hardware description language (VHDL) macro embedded in a single chip device. The VHDL macro comprises digital signal processing (DSP) core logic and on-chip logic analysis (OCLA) logic, which is provided for capturing data processed by the DSP core logic without interrupting operations of the DSP core logic. The OCLA logic is controlled by a host unit externally provided to the single chip device.
Further, another aspect of the present invention is a single chip device comprising a signal processing unit, a plurality of memory blocks and a on-chip logic analysis (OCLA) unit. The OCLA unit captures data processed by the signal processing unit without interrupting operations of the signal processing unit. The OCLA unit is controlled by a host unit externally provided to the single chip device.
A data capturing unit is embedded within the VHDL macro of a single chip device to observe or watch the internal operations of the VHDL macro, thereby enabling non-obtrusive real-time data acquisition for data processed in the VHDL macro without interrupting any internal operation of a signal processing unit.